Embedded Image Processing Project

% setenv CROSS_COMPILE ppc_4xxFP-
% setenv PATH "/opt/eldk-4.2/usr/bin:/opt/eldk-4.2/bin:$PATH"
% git clone git://git.denx.de/u-boot.git
% git-archive --format=tar v2010.03 | bzip2 > ../v2010.03.tbz
% cd ../; mkdir v2010.03; cd v2010.03; tar xvfjp ../v2010.03.tbz
% make canyonlands_config
% make
% cp u-boot.bin /tftpboot/u-boot/u-boot.bin-2010.03
% cd /tftpboot/u-boot; ln -s u-boot.bin-2010.03 u-boot.bin

Turn on the power and the below command on the u-boot prompt
>> run nupd (run the update script)

>> reset

U-Boot 2009.11.1 ( 6月 15 2010 - 14:25:44)

CPU: AMCC PowerPC 460EX Rev. A at 800 MHz (PLB=200 OPB=100 EBC=100)
Security/Kasumi support
Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
Internal PCI arbiter enabled
32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 2*PCIe, Rev. 16
I2C: ready
DRAM: 2 GB (ECC not enabled, 400 MHz, CL3)
FLASH: 64 MB
NAND: 128 MiB
PCI: Bus Dev VenId DevId Class Int
00 06 1095 3124 0180 00
PCIE0: successfully set as root-complex
02 00 10ee 5050 0500 ff
PCIE1: link is not up.
DTT: 1 is 47 C
Net: ppc_4xx_eth0, ppc_4xx_eth1

Type run flash_nfs to mount root filesystem over NFS

Hit any key to stop autoboot: 0
>>

I had the compilation error about the xps_ii_temac core as the following:

ERROR:Xst:1484 - A core is unlicensed!

The license has expired several months ago. I installed the soft core for the virtex5 LX100T.

AR 32054: XPS_LL_TEMAC_v1_01 - INFO:coreutil - License for component not found
http://www.xilinx.com/support/answers/32054.htm

AR29828: 10.1 EDK - Why does the xps_ll_temac result in an evaluation license warning?
http://www.xilinx.com/support/answers/29828.htm

We use the expantion connectors on the ML509 board to attach the image sensor as below:
J5: a power supply connector
J6: an expantion connector for the MT9P031 image sensor

Pin assign of the JP5 and JP6 connector on page 11 in the ML509 board schematic

--------------------------------------
Power Supply Connectors
--------------------------------------

J5 Pin Label FPGA Pin Description
1 VCC5 5V Power Supply
2 VCC5 5V Power Supply
3 VCC5 5V Power Supply
4 VCC5 5V Power Supply
5 NC Not Connected
6 VCC3V3 3.3V Power Supply
7 VCC3V3 3.3V Power Supply
8 VCC3V3 3.3V Power Supply
9 VCC3V3 3.3V Power Supply
10 NC Not Connected

--------------------------------------
Single-Ended Expansion I/O Connectors
--------------------------------------

Header J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits the signals on this connector to carry high-speed, single-ended data. All single-ended signals on connector J6 are matched length traces. The VCCIO of these signals can be set to 2.5V or 3.3V by setting jumper J20. Table 1-10 summarizes the single-ended connections on this expansion I/O connector.

Table 1-10: Expansion I/O Single-Ended Connections (J6)

J6 Pin Schematic Net Name FPGA Pin

Board label, Signal name, FPGA Pin, MT9P031 Pin
2 HDR1_2 H33 SCL
4 HDR1_4 F34 SDA
6 HDR1_6 H34 RESET
8 HDR1_8 G33 PXL_CLK
10 HDR1_10 G32 F_VALID
12 HDR1_12 H32 L_VALID
14 HDR1_14 J32 D<11>
16 HDR1_16 J34 D<10>
18 HDR1_18 L33 D<9>
20 HDR1_20 M32 D<8>
22 HDR1_22 P34 D<7>
24 HDR1_24 N34 D<6>
26 HDR1_26 AA34 D<5>
28 HDR1_28 AD32 D<2>
30 HDR1_30 Y34 D<4>
32 HDR1_32 Y32 D<1>
34 HDR1_34 W32 D<3>
36 HDR1_36 AH34 D<0>
38 HDR1_38 AE32
40 HDR1_40 AG32
42 HDR1_42 AH32
44 HDR1_44 AK34
46 HDR1_46 AK33
48 HDR1_48 AJ32
50 HDR1_50 AK32
52 HDR1_52 AL34
54 HDR1_54 AL33
56 HDR1_56 AM33
58 HDR1_58 AJ34
60 HDR1_60 AM32
62 HDR1_62 AN34
64 HDR1_64 AN33